The present invention relates to a high frequency amplifier circuit which is capable of a wide range of gain control.
In recent years, together with developments which have been made in "new media" apparatus such as CATV, etc., requirements have arisen for high frequency amplifier circuits having enhanced performance. An example of a prior art high frequency amplifier circuit will be described referring to FIGS. 1 and 2 of the drawings. FIG. 1 is a circuit diagram of an example of a prior art high frequency amplifier circuit, while FIG. 2 shows a typical characteristic of gain reduction with respect to cross modulation for such a circuit. In FIG. 1 numeral 8 denotes a dual-gate FET (field effect transistor) which is designed for high-frequency operation, 14, 9 and 4 are by-pass capacitors each having a large value of capacitance (e.g. 1,000 to 2,000 pf). Numeral 6 denotes a feedback capacitor, 16 a feedback resistor, 13 and 10 denote bias resistors, 7 a zener diode and 5 denotes a choke coil serving as a load. Numeral 1A denotes a high frequency signal input terminal, 1B an A.G.C. (automatic gain control) voltage input terminal, 1C denotes a high frequency signal output terminal, 1D a first power supply terminal and 1E a second power supply terminal.
The operation of this prior art high frequency amplifier circuit is as follows. A high frequency input signal is transferred from the input terminal 1A through the capacitor 11 to the first gate electrode G.sub.1 of the FET 8. A DC current flows from the source electrode S of the FET 8 through the resistor 12 to then flow through the zener diode 7. A fixed voltage thereby appears at the cathode of the zener diode 7 which is applied through the resistor 13 to the first gate electrode G.sub.1 of the FET 8. A feedback circuit consisting of the resistor 16 in series with the feedback capacitor 6 is connected between the drain electrode D and the first gate electrode G.sub.1 of FET 8, to ensure uniform amplification over a wide frequency range. The drain electrode D is coupled to receive a supply voltage V.sub.1 which is supplied through the choke coil 5, while the high frequency output signal that is produced from the drain electrode D is coupled through the capacitor 4 to the output terminal 1C, to be supplied to a succeeding circuit stage. An A.G.C. voltage is supplied from the A.G.C. voltage input terminal 1B to the second gate electrode G.sub.2 of FET 8, to control the circuit gain.
The gain reduction/cross modulation characteristic of this circuit is indicated as curve 9B in FIG. 2, in which amounts of gain reduction (i.e. resulting from application of the A.G.C. voltage) are plotted along the horizontal axis, while cross modulation rejection is plotted along the vertical axis. It is assumed that point 9C in FIG. 2 corresponds to the A.G.C. delay point, i.e. the point at which A.G.C. operation begins. By drawing a line from point 9C at an angle of 45.degree., as shown, a point of intersection 9A is obtained with the cross modulation characteristic curve 9B. This point 9A corresponds to a condition whereby any further increase in gain control (i.e. increased degree of gain reduction by application of A.G.C.) will result in interference being produced by an interfering signal whose level is identical to that of the desired signal.
It will thus be apparent that with a prior art high frequency amplifier circuit of the form described above, severe cross-modulation effects are produced when the degree of gain reduction effected by A.G.C. control exceeds a certain value.